Design of 16 Bit Carry Look Ahead Adder Using Reversible Logic

The demand of low power high speed circuits are in demand with the increasing universal growth in electronic system and the loss of information is not acceptable as with single loss of a bit information the energy loss is equal to kTlog2 joules/bit. Reversible logic can be of prominent interest to design low power arithmetic and data path units for digital signal processing applications, such as the designs of low power adders, multipliers, FFT, IDCT etc, and quantum computers. Quantum logic gates perform an elementary unitary operation and any unitary operation is reversible, hence quantum networks effecting elementary arithmetic operations must be built from reversible logic components. Thus, reversible logic will also be the immediate requirement to solve DSP problems with quantum computers. And the lowest processing units are adder and subtractor to perform any operation in digital world so in this paper I proposed a carry look ahead adder using reversible logic. And is simulated using Micro-wind 3.1 too on 90nm technology. The delay measured is 47nS and power consumed is .2mW and area acquired is 245μm.